1. Field of the Invention
The present invention relates to a logical circuit for serializing and outputting a plurality of signal bits simultaneously read from a memory cell array or the like, and in particular, a logical circuit with the timing margin of control signals required for the operation control expanded.
2. Description of the Related Art
There is a method for simultaneously specifying a plurality of addresses of a memory cell on the basis of one input address. There is a memory specification, called burst length, in which an address to be selected next is determined on the basis of an input address, and the above-described specifying method is enabled by the burst length. From data stored in a plurality of addresses simultaneously specified, data bits are burst-output in serial. In addition, by the CAS latency standard, the time period front an address input to a start of data bit output to the outside is specified.
FIG. 1 is a block diagram showing the configuration of a conventional logical circuit. This conventional logical circuit is a circuit to which 4-bit signals (burst length: 4) simultaneously addressed from a memory cell array are input in parallel and from which they are burst-output in serial.
As shown in FIG. 1, four input bit lines BL1 through BL4 connected to the memory cell array are provided to the conventional logical circuit. Latch circuits L1 and L5 are connected to the input bit line BL1, latch circuits L2 and L6 are connected to the input bit line BL2, latch circuits L3 and L7 are connected to the input bit line BL3, and latch circuits L4 and L8 are connected to the input bit line BL4. A first latch circuit group is composed of the latch circuits L1 through L4 and a second latch circuit group is composed of the latch circuits L5 through L8.
Switches SW1 and SW5 are respectively provided between the input ends of the latch circuits L1 and L5 and their common connection point. Switches SW1 and SW5 are controlled by control signals t1 and t2, respectively. Switches SW3 and SW7 are respectively provided between the input ends of the latch circuits L3 and L7 and their common connection point. Switches SW3 and SW7 are controlled by the control signals t1 and t2, respectively
Switches SW2 and SW6 are provided respectively between the input ends of the latch circuits L2 and L6 and their common connection point. Switches SW2 and SW6 are controlled by the control signals t1 and t2, respectively. In addition, Switches SW4 and SW8 are respectively provided between the input ends of the latch circuits L4 and L8 and their common connection point. Switches SW4 and SW8 are controlled by the control signals t1 and t2, respectively.
The output ends of the latch circuits L1 through L8 are connected in common to a node N1, and switches SW11 through SW18 are respectively connected between the node N1 and output ends of the latch circuits L1 through L8. The switches SW11 through SW18 are controlled by control signals tA through tH, respectively.
In addition, there is provided an output circuit 101 to which the node N1 is connected. In the output circuit 101, a switch SW21 one end of which is connected to the node N1 is provided. The switch SW21 is controlled by a control signal tZ. The other end of the switch SW21 is connected to the output terminal OUT.
Explanation will be given of operation of the conventional logical circuit configured as described above. FIG. 2 is a timing chart that shows the operation of the conventional logical circuit.
The conventional logical circuit operates in synchronism with an external clock CLK. One cycle of the external clock CLK is, for example, 10 nsec. The CAS latency (CL) is 2, in which, after 2 clocks from input of the address in the memory cell array, data bit stored in the address is output.
When 4-bit data are read out simultaneously from the memory, the 4-bit data are propagated in parallel to input bit lines BL1 through BL4. These data bits are denoted by D1, D2, D3, and D4. Also data bits successively read out thereafter are denoted by D5, D6, D7, D8, . . . Dn. Then, the control signal t1 rises and the switches SW1 through SW4 are turned on. As a result, to the latch circuits L1 through L4, which composes the first latch circuit group, the data bits D1 through D4 are latched, respectively.
Thereafter, the control signals t2 and t1 rise alternately every 1 clock and the data bits D5 through D8 are latched to the latch circuits L5 through L8, which composes the second latch circuit group, respectively, and the data bits D9 through D12 are latched to the latch circuits L1 through L4, respectively, and the data read out from the memory cell array are alternately latched to the latch circuit groups alternately by 4 bits.
In the meantime, on the output side of the latch circuits L1 through L8, the control signals tA, tB, tC, tD, tE, tF, tG and tH rise successively every xc2xc clock of the external clock CLK. The control signal tZ becomes active in synchronism with rising of all the control signals tA through tH. It should be noted that the control signal tA becomes active more than 1 clock faster than the data bits D9 is latched. If the control signal tA becomes active in timing slower than that timing, data will be destroyed because at least the data bits D4 is not output in timing when the data bits D9 through D12 are latched.
In this way, 4-bit data simultaneously read out from the memory cell array are serialized and output.
However, since in the above-mentioned conventional logical circuit, the control signal tZ becomes active in synchronism with rising of all the control signals tA through tH, the length of one cycle of the control signal tZ is xc2xc times as much as the length of one cycle of the external clock CLK, as shown in FIG. 2. If the length of one cycle of the external clock CLK is 10 nsec., the length of one cycle of the control signal tZ is 2.5 nsec., which is extremely short. If the duty ratio is 50%, the activation and deactivation controls must be carried out every 1.25 nsec. Consequently) the timing margin is extremely narrow, causing a problem of difficult control. With respect to the control signals tA through tH, it is not as much as the control signal tZ, but activation and deactivation controls must be carried out every 2.5 nsec., and the timing margin is also narrow.
As described above, in order to simultaneously read out, serialize, and output a plurality of data bits, at least the same number of latch circuits to latching the data as the number of the data bits simultaneously read out is required. When the output of data bit is delayed by the CAS latency standard or a long data retention period is unable to be set, a data bit already latched is destroyed it a next new data bits arrives from the memory cell array before all the data are output from the latch circuits. To prevent this, the number of latch circuits may be increased, but since the longer the burst length or the higher the operation speed, the more increased is the number of simultaneous readouts from the memory cell array, and consequently, the increase of latch circuits as a result of this will become extremely larger and it is not desirable from the viewpoint of space saving, reduced cost and the like. Consequently, all the latched data must be output before new data arrives from the memory cell array by the use of the control signal tZ, which operates at a high speed. However, as described above, there is a problem, in that timing margin of the control signal tZ is extremely narrow and it is difficult to control its activation and deactivation.
It is an object of the present invention to provide a logical circuit that can secure wide timing margin for control signals even under the high-speed operation and that can improve the operation accuracy.
A logical circuit according to the present invention comprises even input bit lines, a first latch circuit group and a second latch circuit group are provided. The first latch circuit group comprises a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the even input bit lines, respectively, in a first timing. The second latch circuit group comprises a plurality of latch circuits which simultaneously latch A plurality of signal bits propagating the even input bit lines, respectively, in a second timing. The output ends of a plurality of latch circuits are wired-OR to a first node, the plurality of latch circuits latching signal bits which propagate one half of the even input bit lines. The output ends of a plurality of latch circuits are wired-OR to a second node, the plurality of latch circuits latching signal bits which propagate remaining one half of the even input bit lines. The first and the second nodes are wired-OR to a third node. The logical circuit further comprises a first control system and second control system. The first control system successively outputs signal bits latched to one latch circuit group of the first and second latch circuit groups to the first node and then successively outputs signal bits latched to the other latch circuit group to the second node before latching the next signal bits. The second control system alternately outputs signal bits successively inputted to the first and second nodes from the first and second nodes to the third node.
In the present invention, the output ends of a plurality of latch circuits are connected to the first and second nodes half-and-half, and signal bits successively input to the first and second nodes are alternately output from both nodes to the third node by the second control system. As a result, the signal bits latched to a plurality of the latch circuits are serialized and output from the third node. In such event, because the second control system is only required to alternately switch the connection between the first and second nodes and the third node, a control signal for the switching is not required to rise every time the signal bit is output. Consequently, a wide timing margin of the control signal can be secured. In addition, even when a latch circuit whose output end is connected to the first node and a latch circuit whose output end is connected to the second node become connecting simultaneously to each node, the data latched to both latch circuits is not output from the third node by the second control system. Therefore, in the first control system, a wide timing margin for a control signal can be secured.